Senior Hardware Engineer / Hardware Architect – High-Speed Board Design

Description

We are seeking a Senior Hardware Engineer to lead the end-to-end design of advanced high-speed boards , from concept and architecture through production and mass manufacturing. This role involves working on cutting-edge interconnect technologies , including 224G SerDes , PCIe Gen5-7 , and DDR5 , while collaborating closely with SI/PI teams, mechanical engineering, firmware, FPGA, and ODM partners . The ideal candidate is a hands-on technical leader with strong system-level thinking and deep board-level expertise.

Key Responsibilities

• Own full hardware lifecycle : system concept, architecture, schematic, layout, bring-up, validation, and production

Lead high-speed board designs supporting

224G SerDes PCIe Gen7 DDR5 (RDIMM/SODIMM/Soldered down )

Drive schematic and layout development using

Cadence OrCAD Capture Cadence Allegro PCB Designer Architect and review power delivery solutions , including: VRM selection and topology Power sequencing and inrush control Load-step response, transient analysis, and efficiency Work closely with Signal Integrity (SI) and Power Integrity (PI) teams on: Channel budgeting, insertion loss, crosstalk Return loss, jitter, equalization strategy Interface with FPGA team , with strong advantage for: Intel (Altera) FPGAs High-speed transceivers and memory interfaces

Collaborate cross-functionally with

Mechanical engineers (form factor, thermal, constraints) Firmware and validation teams Manufacturing and test PCB vendor stackup and materials Lead engagement with ODM / EMS partners , including: Design reviews DFM / DFA / DFT Bring-up and issue resolution Mentor junior engineers and provide technical leadership across the HW team

Requirements

• Required Qualifications
• B.Sc. or M.Sc. in Electrical Engineering (or equivalent)
• 10+ years of hands-on experience in high-speed board design (worked on DC switch)
• Proven experience leading boards from concept to production

Deep knowledge of

High-speed interfaces (PCIe, SerDes, DDR) Multi-rail power architectures and VRMs

Strong proficiency in

OrCAD Capture Cadence Allegro

Solid understanding of

High-speed routing constraints Stack-up design and materials SI/PI fundamentals and validation methodologies Experience working with ODM/manufacturing partners Strong communication and leadership skills

Advantages (Nice to Have) Experience with 224G / 112G / 56G SerDes designs PCIe Gen5 - Gen7 enablement or pre-compliance experience Hands-on experience with Intel (Altera) FPGA platforms Background in Networking, or data-center hardware Experience with compliance testing and high-speed lab equipment